Concepedia

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Computer Engineering

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Parallel Hardware Maturation

1952 - 1981

Parallel architectures and shared-memory interconnects converged toward scalable high-performance computing, emphasizing shuffle-exchange networks, parallel memories, and reconfigurable processor arrays to balance latency, bandwidth, and locality. Reliability and conformance in concurrent hardware and software systems were driven by early work on deadlock analysis, prevention, and formal methods for correctness. High-performance hardware design pursued extreme speed through very-large-scale-integration area-time tradeoffs, multiprocessor ARPA systems, and specialized processors, while coding theory and communications research integrated error control and channel coding into hardware performance, and RF/microwave hardware research emphasized transmission-line behavior and antenna design underpinning signal integrity for early links.

Parallel architectures and shared-memory interconnects converged toward scalable HPC, emphasizing shuffle-exchange networks, parallel memories, and reconfigurable processor arrays to balance latency, bandwidth, and locality [4], [8], [9], [18], [20].

Reliability and conformance in concurrent hardware/software systems driven early work on deadlock analysis, prevention, and algorithmic testing of logic circuits, highlighting formal methods and systematic design for correctness [1], [3], [10], [16], [17].

High-performance hardware design pursued extreme speed through VLSI area-time tradeoffs, multiprocessor ARPA systems, and specialized processors, framing design choices around latency, throughput, and silicon area [2], [12], [14], [15], [20].

Coding theory and communications research integrated error control, channel coding, and signal propagation into computer engineering, addressing erasure channels and convolutional codes for reliability and performance [6], [7], [11].

RF/microwave hardware research emphasized transmission-line behavior and antenna design, underpinning signal integrity and wireless-like links in early computer engineering, including transmission lines and linearly polarized microstrip antennas [11], [14].

Parallel HPC Interconnects Era

1982 - 1988

Memory Hierarchy Latency Hiding

1989 - 1995

Network-on-Chip System-on-Chip Architecture

1996 - 2010

Secure Edge-Cloud Acceleration

2011 - 2017

Secure Edge Intelligence

2018 - 2024